Product SoC Architect

Job Details: Job Description: Join our team as a Senior IPU SoC Architect and drive the architectural vision for cutting-edge Infrastructure Processing Unit (IPU) and Data Processing Unit (DPU) platforms. In this strategic role, you'll define compute, memory, and coherency architectures while ensuring optimal end-to-end performance for next-generation data center solutions. You'll be instrumental in shaping architectural decisions that directly impact product scalability, performance efficiency, power optimization, and programmability at hyperscale deployments. As a technical leader, you'll establish performance benchmarks, guide cross-functional validation efforts, and collaborate with diverse engineering teams to identify system bottlenecks and architect innovative solutions. Your expertise in networking and x86 compute architectures will be crucial in positioning our products for market leadership. This is a high-impact role where you'll influence multi-generational architecture roadmaps, drive company-wide technical decisions, and establish yourself as a recognized authority in the field. Core Responsibilities Architecture Leadership & Strategy SoC Architecture Ownership: Lead comprehensive architecture development for IPU SoCs from initial concept through silicon implementation and post-silicon optimization Strategic Planning: Define multi-generation SoC architecture strategy, including processor selection, cache hierarchies, coherency models, and performance/power optimization Interconnect Design: Architect scalable coherent mesh and interconnect fabrics, optimizing for latency, bandwidth, scalability, and area efficiency across heterogeneous IPU components Memory Subsystem Architecture: Design advanced system memory architectures incorporating DDR/HBM technologies, memory controllers, cache coherency protocols, bandwidth allocation, QoS management, and isolation mechanisms Specialized System Design Virtualization Architecture: Drive SMMU/IOMMU architecture for virtualization-intensive IPU workloads, addressing address translation, ATS/PRI protocols, security boundaries, and multi-tenant isolation Workload Translation: Convert complex cloud, networking, storage, security, and virtualization requirements into actionable architectural specifications and design targets Trade-off Analysis: Conduct comprehensive architecture studies balancing performance, power consumption, silicon area, cost implications, and software compatibility Performance Engineering & Validation Establish representative, scalable performance benchmarks for IPU/DPU applications including cloud networking offloads, service chaining, storage acceleration, security processing, virtualization, telemetry, and control-plane operations KPI Development: Transform product requirements into measurable performance indicators and success metrics Testing Methodologies: Create comprehensive workload testing frameworks covering steady-state operations, burst scenarios, microbenchmarks, and end-to-end system validation, including stress testing and edge cases Performance Standards: Develop and maintain performance specifications, acceptance criteria, and release gate metrics Technical Leadership & Collaboration Cross-functional Leadership: Provide technical guidance across silicon design, firmware development, operating system integration, driver development, and system architecture teams Results Analysis: Lead complex performance analysis initiatives, identify root causes of bottlenecks, and propose architectural solutions to meet product objectives Ability to work autonomously while driving alignment across multiple engineering teams Strong communication and influence capabilities with experience driving architectural consensus among diverse stakeholders Qualifications: The Minimum qualifications are required to be initially considered for this position.  Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Batchelor’s degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study 8+ years of SoC, CPU, or subsystem architecture experience with proven leadership in compute and/or memory system design 8+ years of experience in networking performance engineering, systems performance optimization, or SoC/IPU/DPU architecture roles Experience in high-speed Ethernet, packet processing, and data center networking technologies Experience defining and executing performance workload methodologies, KPI-driven validation processes, analyzing complex performance data, identify root causes, and architect effective solutions. Preferred Qualifications Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study ARM/x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or largescale platform architectures. Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments Familiarity with PCIe, CXL, and memory semantics for high performance IO. Experience with performance modeling Techniques (e.g. analytical modeling, simulation, emulation, profiling, and microbenchmarking) Track record of multi generation architectural ownership and mentoring other architects.            Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.     Annual Salary Range for jobs which could be performed in the US: $190,610.00-311,890.00 USD     The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.     Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.