Senior Analog Mixed Signals Engineer - Data Converters Expert

Senior Analog Mixed-Signal IC Designer – Data Converters NXP’s AI and Chip Engineering (ACE) organization provides advanced engineering capabilities and reusable semiconductor IP to all NXP product lines. Within ACE, the specialized Data Converter team develops high-performance analog and mixed-signal IP for a broad range of products, technology platforms, and application domains. Our ADC and DAC solutions form the critical interface between the analog world and digital processing. They support applications such as automotive radar and sensing, vehicle electrification, advanced driver assistance, industrial automation, secure connectivity, wireless and wired communication, audio, edge processing, and IoT. The team develops scalable, configurable, and reusable data converter IP that enables competitive system performance, reduces development time, and supports efficient integration across NXP. By working closely with product-line and SoC teams, we translate diverse application requirements into robust, silicon-proven IP solutions that can be reused across products and technology generations. In this role, you will be a senior member of the Data Converter team. You will operate with a high degree of technical independence, take end-to-end ownership of complex designs, and lead a small technical team when required—from architecture definition and transistor-level implementation through verification, layout realization, IP integration, and silicon evaluation. Your mission is to strengthen NXP’s data converter capability by delivering state-of-the-art IP, driving technical innovation, maximizing reuse across product lines, and providing technical leadership within multidisciplinary development teams. Your Responsibilities Architect, design, and verify state-of-the-art ADCs, DACs, reference circuits, sampling networks, clocking circuits, calibration functions, and supporting analog building blocks. Take end-to-end technical ownership of complex circuit blocks or complete data converter IP, from initial concept and architecture trade-offs through layout, silicon validation, and IP release. Lead a small technical team of analog, mixed-signal, digital, and layout engineers, providing technical direction, coordinating activities, reviewing results, and driving the team toward agreed quality, performance, and schedule objectives. Translate system and product needs into clear IP specifications, performance budgets, interface definitions, verification plans, and integration requirements. Develop robust solutions that meet demanding requirements for performance, power, area, noise, linearity, bandwidth, reliability, and testability across process, voltage, temperature, aging, and mismatch variations. Develop scalable and configurable data converter architectures while maximizing the reuse of circuits, models, verification environments, documentation, and design knowledge across NXP product lines. Lead design reviews and independently drive technical decisions, risk mitigation, and the resolution of complex design, layout, verification, and integration issues. Collaborate with system architects, product-line representatives, SoC teams, digital designers, layout engineers, verification engineers, and test engineers to ensure successful IP integration, qualification, and silicon bring-up. Drive innovation and contribute to technical roadmaps, patents, coaching, and continuous improvement of engineering practices. Your Profile Master’s or PhD degree in Electrical Engineering, Microelectronics, Integrated Circuit Design. Minimum of 12 years of industry related experience, ideal candidate has 15+. Extensive professional experience in analog and mixed-signal IC design, with substantial hands-on expertise and passion for high-performance ADC and/or DAC development. Proven ability to independently architect, design, verify, and debug complex analog and mixed-signal circuits from specification through silicon validation. Strong understanding of data converter fundamentals, converter architectures, calibration techniques, signal-chain budgeting, and power-performance-area optimization. Hands-on experience with converter architectures such as SAR, pipeline, sigma-delta, time-interleaved or hybrid ADCs, and current-steering, voltage-mode, or other advanced DAC architectures. Strong experience with full-custom analog design and verification tools, preferably including Cadence Virtuoso, Spectre, ADE Explorer/Assembler, AMS, MATLAB, Python, and SKILL. In-depth understanding of high-performance analog layout, advanced CMOS technologies, PVT and mismatch analysis, reliability, and post-layout verification. Demonstrated technical leadership, ownership, and communication skills, including the ability to lead a small technical team, guide designers, coordinate multidisciplinary activities, and collaborate effectively across sites. Your Contribution You combine deep analog and mixed-signal circuit expertise with a strong understanding of data converter architectures and system-level requirements. You independently drive technically challenging assignments from concept to silicon-proven implementation and can lead a small technical team toward successful delivery. Beyond your own designs, you provide technical direction, coach engineers, coordinate multidisciplinary activities, and help teams make robust technical decisions. You are motivated to create not only solutions for individual projects, but also scalable architectures, reusable IP, and engineering knowledge that strengthen NXP’s data converter capability across product lines. More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #LI-6692